The wide utilization of cellular and wireless devices drives the rapid development of radio frequency (RF) technologies. The substrates on which RF devices are fabricated play an important role in achieving high level performance in the RF technologies. Fabrications of the RF devices on conventional silicon substrates may benefit from low cost of silicon materials, a large scale capacity of wafer production, well-established semiconductor design tools, and well-established semiconductor manufacturing techniques.
Despite the benefits of using conventional silicon substrates for RF device fabrication, it is well known in the industry that the conventional silicon substrates may have two undesirable properties for the RF devices: harmonic distortion and low resistivity values. Harmonic distortion is a critical impediment to achieve high level linearity in the RF devices built over silicon substrates. In addition, the low resistivity encountered in the silicon substrates may degrade quality factors (Q) at high frequencies of microelectromechanical systems (MEMS) or other passive components.
Further, high speed and high performance transistors are more densely integrated in RF devices, even as they are required to carry more power. Consequently, the amount of heat generated by the RF devices will increase significantly due to the large amount of power passing through the transistors, the large number of transistors integrated in the RF devices, and the high operation speed of the transistors. Accordingly, it is desirable to package the RF devices in a configuration for better heat dissipation.
Wafer-level fan-out (WLFO) packaging technology and embedded wafer-level ball grid array (EWLB) technology currently attract substantial attention in portable RF applications. WLFO and EWLB technologies are designed to provide high density input/output ports (I/O) as well as low profile package height without increasing the size of the component semiconductor chips. The I/O pad size on the chip remains small keeping die size to a minimum. This capability allows for densely packaging the RF devices within a single wafer.
To accommodate the increased heat generation of the RF devices, to reduce deleterious harmonic distortion of the RF devices, and to utilize advantages of WLFO/EWLB packaging technologies, it is therefore an object of the present disclosure to provide a packaging process for a wafer-level package with enhanced thermal and electrical performance.